1. Field of the Invention
The present invention relates to a DC balance offset adjustable circuit and a semiconductor device including this DC balance offset adjusting circuit. The invention more particularly relates to an effective technology for improvement of bit error rate (BER) by dynamically controlling DC offset of a receiver circuit included in a semiconductor device used for high-speed transmission, wherein the DC offset of the receiver can be adjusted in accordance with DC offset in an arbitrary section of received data.
2. Background Art
For high-speed serial transmission between devices (LSI-LSI), the 8 B10 B encode system has been generally used because of the advantages of this system, such as stability behavior (consecutive 5 bits or shorter) of a clock data recovery (CDR) circuit and reduction of data dependent jitter. However, the use of encode systems such as 64 B/66 B, 64 B/67 B, and 128 B/130 B having an increased unit data length is currently prevailing with recent increases of the transmission rate.
The use of an encode system having a longer unit data length can raise the effective transmission rate higher than that of 8 B10 B system, resulting in a 20% difference in the transmission rate. In this case, however, the DC balance of H/L compensated ½ (DC level) for 8 B10 B collapses in a certain section of received data, and generates DC offset.
Generally, DC balance is kept at ½ (DC level) in a pseudo random pattern (PRBS). According to a long data pattern such as PRBS23 and PRBS31, DC offset becomes significant and deteriorates BER in a section of data around a range from 100 to 1,000 bits.
For adjustment of DC offset, there are two systems currently employed: one performs automatic adjustment by calibration at the time of power on of an LSI; and the other performs automatic and dynamic adjustment for data patterns.
The invention has been developed to provide dynamic DC offset adjustment for data patterns. A typical example of related art associated with this adjustment is shown in JP-A-10-341261.
This reference discloses a method which removes offset from a reference level based on the phase difference between a received data pattern and a clock recovered from the data pattern.
According to the technology disclosed in JP-A-10-341261, the DC offset of a receiver can be dynamically adjusted relative to a DC offset value corresponding to the phase difference of the received data, but it is difficult to adjust relative to DC balance in an arbitrary section of the received data.
Generally, a worst case bit pattern of received data in a high-speed transmission system is dependent on characteristics of a transmission channel (loss, reflection, and distance) and performance of a receiver circuit (receiver, equalizer, and CDR) and the like. Thus, according to some high-speed transmission specifications, a tolerance test for each data pattern is evaluated based on a reference transmission loss determined beforehand.
In a system allowing transmission at BER<1×E−12 between LSI-LSI, errors have been observed in an arbitrary section of data. These errors are considered to have been produced by biasing of DC offset.
This system meets the specifications for the receiver jitter tolerance. However, examination of the error locations in the data pattern shows that the data pattern has no worst pattern (such as solitary waves) of PRBS, but contains errors generated with repeatability in a section integrating each data pattern of around 100 to 1,000 bits and generating biasing of DC offset.